The present inventive concept relates to semiconductor memory devices and methods of operating the same.
Nonvolatile memory devices have the capability of retaining stored data in the absence of applied power. There are different types of nonvolatile memory devices. However, so-called flash memory, including several types of electrically erasable nonvolatile memory, has become an important component of many contemporary digital data and consumer electronics devices. NAND type flash memory is configured using a plurality of memory strings, wherein each memory string includes a plurality of series-connected memory cells arranged between intersecting bit lines and word lines.
Figure (FIG. 7 is a partial schematic view of a typical NAND flash memory. The memory cell array shown in FIG. 7 includes N+1 bit lines (BL0-BLN), n+1 word lines (WL0-WLn), and N+1 memory strings (ST0-STN) connected between a common source line CSL and a corresponding bit line BL. Each memory string ST includes n+1 series-connected nonvolatile memory cells (MC0-MCn). Each nonvolatile memory cell MC is assumed to have a floating gate structure that may be electrically rewritten to a desired data state.
Within this configuration, the drain of each memory cell MCn is connected to a corresponding bit line BL0 through a string select transistor SS1. The source of memory cell MC0 is connected to a common source line CSL through a ground select transistor GS1. Control gates of the memory cells MC in a particular row are commonly connected to a word line WL.
In the memory cell array of FIG. 7, an erase operation is performed by applying a high voltage (e.g., 20V) to a constituent semiconductor substrate while applying 0V to the word lines WL0-WLn. Under these voltage conditions, electrons are removed from a floating gate (i.e., an electrical charge accumulation layer) typically formed of polysilicon. In this manner, the threshold voltage of memory cell MC may be set to an erase threshold voltage VthL (e.g., −1V).
During a write (or programming) operation, electrons are injected onto the floating gate from the semiconductor substrate by applying 0V to the semiconductor substrate while a high voltage (e.g., 20V) is applied to the control gate (selected word line WL). In this manner, the threshold voltage of memory cell MC may be increased from the erase threshold voltage VthL.
Certain data values are ascribed to respective programmed threshold voltage states. In a binary memory cell MC, a data value of “1” may be ascribed to the erase threshold voltage VthL, and a data value of “0” may be ascribed to a higher (programmed) threshold voltage VthH (e.g., 3V).
During a read operation directed to a particular memory cell, after pre-charging all of the bit lines (BL0-BLN) to a predetermined voltage, a read voltage (e.g., 2V) between the higher threshold voltage VthH and the erase threshold voltage VthL is applied to a control gate of selected memory cell through the word line connected to a memory cell MC. A voltage higher than the read voltage is applied to control gates of memory cells MC except the selected memory cell, the string select transistor SS1 and the ground select transistor GS1. The memory cells MC except the selected memory cell, the string select transistor SS1 and the ground select transistor GS1 are turned ON.
When a data value for the selected memory cell is “1”, a cell current flows through the corresponding memory cell. When a data value for the selected memory cell is “0”, the cell current does not flow. Thus, the written data value for a selected memory cell may be read on the basis of whether or not the cell current flows in response to the read operation voltage conditions.
During a read operation in the memory cell array of NAND flash memory shown in FIG. 7, the voltage of the common source line CSL increases according to the amount of current flowing from each memory string to the common source line CSL. As a result, the threshold voltage of the selected memory cell may unintentionally change. That is, a voltage increase on the common source line CSL may drive the voltage of the common source line CSL above ground voltage due to the voltage drop caused by current flowing to the common source line CSL and a parasitic resistance inherent in the common source line CSL.
For example, in the memory cell array of the NAND type memory cell shown in FIG. 7, it is assumed that a data value of “0” has been written to selected memory cells MCa, MCb and MCc. Then, a verify read operation is performed on the selected memory cells MCa, MCb and MCc. It is further assumed that each of the memory cells MCa, MCb and MCc is insufficiently written, a threshold voltage Vtha of the memory cell MCa is equal to a threshold voltage Vthb of the memory cell MCb and a threshold voltage Vthc of the memory cell MCc is greater than the threshold voltage Vtha and the threshold voltage Vthb (i.e., Vtha=Vthb<Vthc). Finally, it is assumed that each of the threshold voltages Vtha, Vthb and Vthc is less than a verifying read voltage Vvfy which will be described later (i.e., Vtha, Vthb, Vthc<Vvfy).
Under these assumptions, the verifying read voltage Vvfy is applied to a word line WL commonly connected to control gates of the memory cells MCa, MCb and MCc. A read voltage Vread is applied to other word lines WL. Memory cells connected to the word line WL to which the read voltage Vread is applied enter a pass state (i.e., a state wherein current may flow). The string select transistor SS1 and the ground select transistor GS1 are turned ON.
The verifying read voltage Vvfy is applied to the control gates of the memory cells MCa, MCb and MCc. Since the verifying read voltage Vvfy is greater than the threshold voltages Vtha, Vthb and Vthc, the memory cells MCa, MCb and MCc will be turned ON.
However, when the verifying read voltage Vvfy is applied, the memory cells MCa and MCB having the threshold voltages Vtha and Vthb less than the threshold voltage Vthc of the memory cell MCc are turned ON first. A cell current Ia and a cell current Ib flow in the common source line CSL through the memory cells MCa and MCb. At this time, a voltage increase (referred to as “CLS noise”) on the common source line CSL having a parasitic resistance occurs.
A voltage VGS between a gate and a source of the memory cell MCc and a voltage VDS between a drain and a source of the memory cell MCc are reduced (i.e., the threshold voltage Vthc becomes relatively high) and thereby a current does not flow through the memory cell MCc. As a result, it becomes difficult if not impossible to correctly determine whether the memory cell MCc is an OFF-cell, despite its (intended) programmed data state of “0”.
FIG. 8, inclusive of FIGS. 8A, 8B, and 8C, further illustrates the effect that the voltage increase (i.e., the CSL noise) on the common source line CSL has on the voltage VGS between the gate and source and the voltage VDS between a drain and a source. In a memory cell MC illustrated in FIG. 8A, when CSL noise does not exist in the common source line CSL. Then, as illustrated in FIG. 8B, a pre-charge voltage of 0.6V is applied to the drain of the memory cell MC through a bit line BL. A voltage of 1.0V is applied to the gate of the memory cell MC through a word line WL. A voltage of 0V is applied to the source via the common source line CSL. Under these assumed conditions, a voltage between the drain and source of the memory cell MC is 0.6V (i.e., VDS=0.6V).
When CSL noise of 0.3V occurs in the common source line CSL, as illustrated in FIG. 8C, the source voltage of the memory cell MC increases by 0.3V. Thus, the voltage VGS between the gate and source of the memory cell MC becomes 0.7V. A voltage VDS between the drain and source of the memory cell MC becomes 0.3V. When CSL noise occurs in the common source line CSL, the voltage VGS and the voltage VDS are reduced and thereby the current flowing through the memory cell MC is reduced.
FIG. 9 is a graph further illustrating the change in drain current relative to the voltage VDS between the drain and source of the memory cell described in FIG. 8. A characteristic curve A represents a case of when CSL noise does not exist and a characteristic curve B represents a case of when CSL noise exists. As illustrated in FIG. 9, even though applying a same word line voltage, the voltage VGS between the gate and source of memory cell is reduced due to the CSL noise and thereby a characteristic curve of drain current varies from a characteristic curve A to a characteristic curve B. Thus, a cell current reduced from a drain current of when the CSL noise does not exists (i.e., a drain current corresponding to a point a1 on the characteristic curve A) to a drain current of when the CSL noise exists (i.e., a drain current corresponding to a point b1 on the characteristic curve B).
Even though a similar word line voltage is applied to a memory cell, if the value of the resulting drain current is slightly lower reduced from the current corresponding to the point al on the characteristic curve A, the programmed state of the memory cell may be misjudged depending upon whether the CSL noise exists or not. That is, a read operation directed to such a memory cell may fail due to the presence of CSL noise.
As described above, when CSL noise exists, the threshold voltage of a read cell is increased, the degree of accuracy for the read operation and write operation may be deteriorated. According to a conventional response, after pre-charging a plurality of bit lines BL before performing a read operation, a dummy read voltage lower than a predetermined read voltage is applied to the plurality of selected memory cells connected to a selected word line. At this time, current flows through a plurality of memory cells connected to an unselected word line. Charge on the bit line BL connected to a selected memory cell having a threshold voltage sufficiently less than a read voltage are discharged through the selected memory cell and the common source line CSL. Thus, the CSL noise is reduced and thereby unintended variations in threshold voltage may be prevented. That is, according to the conventional remedy to the foregoing problem, read operation accuracy may be improved by performing the read operation only after reducing (or eliminating) an accompanying increase in electric potential from the common source line CSL when the CSL noise exists.